1. Field of the Invention
The invention relates to a data driver for an LCD (Liquid Crystal Display) panel, and more particularly to a data driver capable of saving the number of DACs (digital-to-analog converters).
2. Description of the Related Art
Recently, LCDs have been widely used because they have favorable advantages of thinness, lightness and low electromagnetic radiation. It is therefore an important subject in the LCD field to decrease the costs of the LCDs and to increase the product competitiveness.
FIG. 1 is an architecture diagram showing a conventional LCD system. The LCD panel 100 with a resolution of 1024×768 will be described as an example. The LCD panel 100 has 1024×3 data lines that are respectively driven by data drivers 102, and 768 scan lines that are respectively driven by scan drivers 104. If each data driver 102 may drive 384 data lines and each scan driver 104 may drive 256 data lines, the LCD panel 100 requires eight data drivers 102 and three scan drivers 104. The data drivers 102-1 to 102-8 sequentially receive multiple channels of pixel data PD from a controller 106 under the control of a data control signal Cntl_D output from the controller 106. The data drivers 102-1 to 102-8 process the received pixel data PD and then drive multiple data lines of the LCD panel 100. On the other hand, the scan drivers 104 sequentially output scan signals to scan each scan line under the control of a scan control signal Cntl_S output from the controller 106.
FIG. 2 is a circuit block diagram showing the data drivers 102-1 to 102-8 of FIG. 1. The conventional data driver 102 is composed of a shift register 212, a first line buffer 214A, a second line buffer 214B, a digital-to-analog converting circuit 216, and an output buffer 218. The shift register 212 outputs a control signal C. The first line buffer 214A sequentially receives and stores the pixel data PD output from the controller 106 according to the control signal C. After the first line buffer 214A finishes its receiving operations, the first line buffer 214A simultaneously transfers all the pixel data PD stored therein to the second line buffer 214B. The second line buffer 214B simultaneously outputs all the pixel data PD to the digital-to-analog converting circuit 216. The output buffer 218 parallely receives the pixel data PD output from the digital-to-analog converting circuit 216 and also parallely outputs the pixel data PD to the data lines of the LCD panel 100.
The operations of the data drivers 102-1 to 102-8 as shown in FIG. 2 will be further described with reference to an example of the data driver 102-1. It is assumed that the controller 106 outputs two ports of pixel data PD to the line buffer 214-1 at a time, wherein each port of pixel data includes a channel of red pixel data, a channel of blue pixel data, and a channel of green pixel data. That is, the controller 106 outputs six channels of pixel data PD to the line buffer 214-1 at a time. If each channel of pixel data has 8 bits, each of the first line buffer 214A and the second line buffer 214B must have 384×8 bits (i.e., 6×64×8 bits) because the data driver 102-1 has to drive 384 data lines. The controller 106 has to output 6×8 bits of six channels of pixel data at a time. After 64 times of outputs, the pixel data input operations for one data driver 102-1 are completed. After the pixel data receiving operations for one data driver 102 are finished, the pixel data receiving operations for another data driver 102 are started.
After the pixel data receiving operations for the first line buffer 214A-1 are finished, the first line buffer 214A-1 parallely and simultaneously transfers the stored 6×64×8 bits of pixel data PD to the second line buffer 214B-1. Then, the second line buffer 214B-1 simultaneously outputs the pixel data PD to the digital-to-analog converting circuit 216-1. The digital-to-analog converting circuit 216-1 includes 384 DACs (digital-to-analog converters), that is, DAC(1) to DAC(384). Each DAC may convert one channel of pixel data PD. Thus, the digital-to-analog converting circuit 216-1 may simultaneously convert 384 channels (i.e., 6×64×8 bits) of pixel data PD into analog data.
After the digital-to-analog converting circuit 216-1 simultaneously converts the 6×64×8 bits of pixel data PD into the analog data, the digital-to-analog converting circuit 216-1 simultaneously and parallely inputs the 384 channels of analog pixel data PD to the output buffer 218-1. The output buffer 218-1 is composed of multiple OP amplifiers, which may enhance the capability of the 384 channels of analog pixel data PD output from the data driver 102-1 for driving the data lines.
In a general circuit layout, the DACs occupy relatively large area. In each of the conventional data driver 102, because 384 channels of data pixel PD have to be converted into analog data, 384 DACs are required. Consequently, the chip area of the overall data drivers 102 is relatively large and the cost thereof is relatively high. Therefore, it is very important to reduce the area required by the DACs and to reduce the cost.